period_card.cpp

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#include "stdafx.h"

#include "period_card.h"

PeriodCard::PeriodCard(int position, ISISVME* vme, DAEstatus& status) : DAE2Card(position, vme, status)
{
        std::ostringstream message;
    printStatus(message, status);
        status.addInfo(FAC_ENVCARD, message.str());
}

struct period_modes
{
        int bit;
        const char* unset;
        const char* set;
};

static const period_modes mode_list[] = {
        {10, "Extract Trigger Veto Disabled", "Extract Trigger Veto Enabled" },
        {9, "50Hz Veto Disabled", "50Hz Veto Enabled" },
        {8, "Internal Period Clock Mode", "External Period Clock Mode" },
        {7, "", "Multiple Period sequence complete" },
        {6, "Single period sequence mode", "Multiple period sequence mode" },
        {5, "Internal period control mode", "External period control mode" },
        {4, "Non-period mode", "Period mode"},
        {3, "", "Run ended AND period sequence completed" },
        {2, "", "Period sequence complete" },
        {1, "", "End after period sequence complete has been requested" },
};

void PeriodCard::printStatus(std::ostream& os, DAEstatus& status)
{
        DAE2Card::printStatus(os, status);
        isisU32_t value32;
        isisU16_t value16;
        int i, nper;
        os << "This is an PERIOD card" << std::endl;
        os << "Current period number = " << getCurrentPeriodNumber(status) << (inDwellPeriod(status) ? " (DWELL)" : " (DAQ)") << std::endl;
        nper = getNumberOfPeriods(status);
        os << "Number of periods = " << nper << std::endl;
        readRegister(PSCNT, &value16, status);
        os << "Period sequence number = " << value16 << std::endl;
        getExtractTriggerVetoCount(&value32, status);
        os << "Extract trigger veto count = " << value32 << std::endl;
        readRegister(PCREG, &value16, status);
        os << "Summary of period control register" << std::endl;
        for(i=0; i<sizeof(mode_list)/sizeof(period_modes); i++)
        {
                if (value16 & (1 << mode_list[i].bit))
                {
                        os << "Bit " << mode_list[i].bit << " is SET (" <<  mode_list[i].set << ")" << std::endl;
                }
                else
                {
                        os << "Bit " << mode_list[i].bit << " is CLEAR (" <<  mode_list[i].unset << ")" << std::endl;
                }
        }
        isisU16_t* frames_needed = new isisU16_t[nper];
        isisU32_t* good_frames = new isisU32_t[nper];
        isisU32_t* raw_frames = new isisU32_t[nper];
        isisU16_t* dwell_flags = new isisU16_t[nper];
        isisU32_t* outputs = new isisU32_t[nper];
        readPERLUT(dwell_flags, frames_needed, nper, status);
        readOUTLUT(outputs, nper, status);
        getRawFrames(0, nper, raw_frames, status);
        getGoodFrames(0, nper, good_frames, status);
        os << "Summary of period card programming (1st 16 max)" << std::endl;
        for(i=0; i< (nper < 16 ? nper : 16); i++)
        {
                os << "Period " << i << (dwell_flags[i] != 0 ? " (DWELL)" : " (DAQ)") << std::endl; 
                os << "\tRequested frames = " << frames_needed[i] << " logic signal output = 0x" << std::hex << outputs[i] << std::dec << std::endl;
                os << "\tCurrent counters (should always be ZERO for DWELL): raw = " << raw_frames[i] << " good = " << good_frames[i] << std::endl;
        }
        delete[] frames_needed;
        delete[] good_frames;
        delete[] raw_frames;
        delete[] outputs;
        delete[] dwell_flags;
        readRegister(MAT_1, &value32, status); os << "Matt's 0x4 register = " << std::hex << value32 << std::dec << std::endl; 
}

int PeriodCard::setPeriodControlBits(isisU32_t mask, bool preserve, DAEstatus& status)
{
    return setRegisterBits(PCREG, mask, preserve, status);
}

int PeriodCard::clearPeriodControlBits(isisU32_t mask, DAEstatus& status)
{
        return clearRegisterBits(PCREG, mask, status);
}

int PeriodCard::setAndClearPeriodControlBits(isisU32_t mask, bool preserve, DAEstatus& status)
{
        return setAndClearRegisterBits(PCREG, mask, preserve, status);
}

int PeriodCard::clearVetoCounters(DAEstatus& status) 
{ 
        return setAndClearPeriodControlBits(PCCLRVETO, true, status); 
}

int PeriodCard::getExtractTriggerVetoCountLow(isisU16_t* value, DAEstatus& status) 
{ 
        return readRegister(EXTTRIGVC0, value, status); 
}

int PeriodCard::getExtractTriggerVetoCountHigh(isisU16_t* value, DAEstatus& status)
{ 
        return readRegister(EXTTRIGVC1, value, status); 
}

int PeriodCard::getExtractTriggerVetoCount(isisU32_t* value, DAEstatus& status)
{
        return readRegister16As32(EXTTRIGVC0, EXTTRIGVC1, value, status);
}

int PeriodCard::enableExtractTriggerVeto(DAEstatus& status) 
{ 
        return setPeriodControlBits(PCEXTTRIG, true, status); 
}

int PeriodCard::disableExtractTriggerVeto(DAEstatus& status) 
{ 
        return clearPeriodControlBits(PCEXTTRIG, status); 
}

int PeriodCard::lookupAccessOUTLUT(DAEstatus& status)
{ 
        return writeRegister16(LOOKTAR, TAROUTLUT, status); 
}

int PeriodCard::lookupAccessPERLUT(DAEstatus& status) 
{ 
        return writeRegister16(LOOKTAR, TARPERLUT, status); 
}

int PeriodCard::lookupFinished(DAEstatus& status)
{ 
        return writeRegister16(LOOKTAR, 0, status); 
}

int PeriodCard::getCurrentPeriodNumber(DAEstatus& status)
{
        isisU16_t period;
        int stat = readRegister(MPCNT, &period, status);
        period &= 0x3fff;
        return period;
}

bool PeriodCard::inDwellPeriod(DAEstatus& status)
{
        isisU16_t period;
        readRegister(MPCNT, &period, status);
        return ((period & (1 << 14)) != 0);
}

int PeriodCard::setNumberOfPeriods(isisU16_t n, DAEstatus& status)
{
        return writeRegister16(MPLIM, n-1, status);  // as this is a period number limit register
}

int PeriodCard::getNumberOfPeriods(DAEstatus& status)
{
        isisU16_t n;
        readRegister(MPLIM, &n, status);
        if (n >= MAX_NUM_PERIODS)
        {
                return MAX_NUM_PERIODS;
        }
        else
        {
                return n+1; // as this is a period number limit register
        }
}

int PeriodCard::getCurrentPeriodSequence(DAEstatus& status)
{
        isisU16_t n;
        readRegister(PSCNT, &n, status);
        return n;
}

int PeriodCard::resetCard(DAEstatus& status)
{
//      setAndClearRegisterBits(MAT_1, (1 << 12), true, status);
        setAndClearPeriodControlBits(PCRESET, true, status);
        return writeRegister(MAT_1, 0, status); // raise veto to disable data collection
}

int PeriodCard::clearPeriodCounters(DAEstatus& status)
{
//      setAndClearRegisterBits(MAT_1, (1 << 12), true, status);
        return setAndClearPeriodControlBits(PCCLRPC, true, status);
}

int PeriodCard::enable50HzVeto(DAEstatus& status)
{
        return setPeriodControlBits(PC50HZENAB, true, status);
}

int PeriodCard::disable50HzVeto(DAEstatus& status)
{
        return clearPeriodControlBits(PC50HZENAB, status);
}

int PeriodCard::setInternalPeriodClockMode(DAEstatus& status)
{
        return clearPeriodControlBits(PCEXTPERCLK, status);
}

int PeriodCard::setExternalPeriodClockMode(DAEstatus& status)
{
        return setPeriodControlBits(PCEXTPERCLK, true, status);
}

int PeriodCard::setSinglePeriodSequenceMode(DAEstatus& status)
{
        return clearPeriodControlBits(PCMULENAB, status);
}

int PeriodCard::setMultiplePeriodSequenceMode(DAEstatus& status)
{
        return setPeriodControlBits(PCMULENAB, true, status);
}

int PeriodCard::setInternalPeriodControlMode(DAEstatus& status)
{
        return clearPeriodControlBits(PCEXTENAB, status);
}

int PeriodCard::setExternalPeriodControlMode(DAEstatus& status)
{
        return setPeriodControlBits(PCEXTENAB, true, status);
}

int PeriodCard::enablePeriodMode(DAEstatus& status)
{
        return setPeriodControlBits(PCENAB, true, status);
}

int PeriodCard::disablePeriodMode(DAEstatus& status)
{
        return clearPeriodControlBits(PCENAB, status);
}

int PeriodCard::endRunAfterSequenceCompletes(DAEstatus& status)
{
        return setPeriodControlBits(PCENDAFTER, true, status);
}

bool PeriodCard::isRunEndedAndSequenceComplete(DAEstatus& status)
{
        isisU16_t value;
        readRegister(PCREG, &value, status);
        if (value & PCENDSEQCOMP)
        {
                clearPeriodControlBits(PCENDAFTER, status);
                return true;
        }
        else
        {
                return false;
        }
}

void PeriodCard::abortSequenceCompleteWait(DAEstatus& status)
{
        clearPeriodControlBits(PCENDAFTER, status);
}

// dwell_flag is 0 for DAQ period, 1 for DWELL period
int PeriodCard::programPERLUT(isisU16_t* dwell_flags, isisU16_t* frames, int nperiod, DAEstatus& status)
{
        int i;
        isisU32_t* pdata = new isisU32_t[nperiod];
        for(i=0; i<nperiod; i++)
        {
                if (frames[i] > 0)
                {
                        pdata[i] = ((frames[i] - 1) & 0xffff) + (dwell_flags[i] != 0 ? (1 << 31) : 0);
                }
                else
                {
                        pdata[i] = ((frames[i]) & 0xffff) + (dwell_flags[i] != 0 ? (1 << 31) : 0);
                }
        }
        lookupAccessPERLUT(status);
        zeroMemory(PERLUTSTART, PERLUTSIZE, 0xffffffff, false, false, status);
        writeMemory(PERLUTSTART, pdata, nperiod, 0xffffffff, false, false, status);
        lookupFinished(status);
        delete []pdata;
        return 0;
}

int PeriodCard::readPERLUT(isisU16_t* dwell_flags, isisU16_t* frames, int nperiod, DAEstatus& status)
{
        int i;
        isisU32_t* pdata = new isisU32_t[nperiod];
        lookupAccessPERLUT(status);
        readMemory(PERLUTSTART, pdata, nperiod, false, false, status);
        lookupFinished(status);
        for(i=0; i<nperiod; i++)
        {
                frames[i] = (isisU16_t)((pdata[i] & 0xffff) + 1); // remove dwell flag
                dwell_flags[i] = ( (pdata[i] & (1 << 31)) ? 1 : 0 );
        }
        delete []pdata;
        return 0;
}

// may also need to duplicate up last value in location n+1
// in case counter in DAE increemnts too far briefly before reset
int PeriodCard::programOUTLUT(isisU32_t* outputs, int nperiod, DAEstatus& status)
{
        isisU32_t tmp32;
        lookupAccessOUTLUT(status);
        zeroMemory(OUTLUTSTART, OUTLUTSIZE, 0xffffffff, false, false, status);
        writeMemory(OUTLUTSTART, outputs, nperiod, 0xffffffff, false, false, status);
// also write last output value to n+1 location; this is a workaround to catch the small
// amout of time that it might get read between a period increment and a period reset
//      tmp32 = outputs[nperiod-1];  // write last value again
        tmp32 = 4;  // debug value for Matt Roberts
        writeMemory(OUTLUTSTART + 4*nperiod, &tmp32, 1, 0xffffffff, false, false, status);
        lookupFinished(status);
        return 0;
}

int PeriodCard::readOUTLUT(isisU32_t* outputs, int nperiod, DAEstatus& status)
{
        int i;
        lookupAccessOUTLUT(status);
// we seem to need to start the outlut at address+1
        readMemory(OUTLUTSTART, outputs, nperiod, false, false, status);
        lookupFinished(status);
        for(i=0; i<nperiod; i++)
        {
                outputs[i] &= 0xffff; // remove junk from top 16 bits
        }
        return 0;
}

int PeriodCard::zeroPeriodFrameCounters(DAEstatus& status)
{
        zeroMemory(RFCNT0START, RFCNT0SIZE, 0xffffffff, false, false, status);
        zeroMemory(GFCNT0START, GFCNT0SIZE, 0xffffffff, false, false, status);
        return 0;
}

int PeriodCard::getPeriodRawFrames(int period, isisU32_t* frames, DAEstatus& status)
{
        return getRawFrames(period, 1, frames, status);
}

int PeriodCard::getPeriodGoodFrames(int period, isisU32_t* frames, DAEstatus& status)
{
        return getGoodFrames(period, 1, frames, status);
}

int PeriodCard::getPeriodRequestedFrames(int period, isisU32_t* frames, DAEstatus& status)
{
        return getRequestedFrames(period, 1, frames, status);
}

int PeriodCard::getRequestedFrames(int period_start, int nperiod, isisU32_t frames[], DAEstatus& status)
{
        int i;
        lookupAccessPERLUT(status);
        readMemory(PERLUTSTART+4*period_start, frames, nperiod, false, false, status);
        lookupFinished(status);
        for(i=0; i<nperiod; i++)
        {
                frames[i] = ((frames[i] & 0xffff) + 1);  // remove dwell flag
        }
        return 0;
}

int PeriodCard::getRawFrames(int period_start, int nperiod, isisU32_t frames[], DAEstatus& status)
{
        int seq = getCurrentPeriodSequence(status);
    isisU32_t* req_frames = new isisU32_t[nperiod];
        getRequestedFrames(period_start, nperiod, req_frames, status);
        readMemory(RFCNT0START + 4*period_start, frames, nperiod, false, false, status);
// not needed now
//      for(i=0; i<nperiod; i++)
//      {
//              frames[i] += (seq * req_frames[i]);
//      }
        delete[] req_frames;
        return status.result();
}

int PeriodCard::getGoodFrames(int period_start, int nperiod, isisU32_t frames[], DAEstatus& status)
{
        int seq = getCurrentPeriodSequence(status);
    isisU32_t* req_frames = new isisU32_t[nperiod];
        getRequestedFrames(period_start, nperiod, req_frames, status);
        readMemory(GFCNT0START + 4*period_start, frames, nperiod, false, false, status);
// not needed now
//      for(i=0; i<nperiod; i++)
//      {
//              frames[i] += (seq * req_frames[i]);
//      }
        delete[] req_frames;
        return status.result();
}

int PeriodCard::startDataCollection(DAEstatus& status)
{
        return setRegisterBits(MAT_1, (1 << 4), true, status);
}
        
int PeriodCard::stopDataCollection(DAEstatus& status)
{
        return clearRegisterBits(MAT_1, (1 << 4), status);
}