env_period_registers_dae3.h

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#ifndef ENV_PERIOD_REGISTERS_DAE3_H
#define ENV_PERIOD_REGISTERS_DAE3_H

class DAE3EnvPeriodPolicy : public DAE3CardPolicy
{
protected:
                static const std::string env_period_policy_name;  
//static const unsigned ECMEMSTART =              0x0;

static const unsigned   FCOUNTR =         0x00; 
static const unsigned   FCOUNTG =             0x04;     
static const unsigned   PCOUNTR0 =            0x08;     
static const unsigned   PCOUNTR1 =            0x0C;     
static const unsigned   PCOUNTG0 =            0x10;     
static const unsigned   PCOUNTG1 =            0x14;     
static const unsigned   SCHPULSE =                0x18;  

static const unsigned FIFOVETFRM =        0x100; 
static const unsigned SMPVETFRM =         0x104;
static const unsigned INTVETFRM =         0x108;  
static const unsigned TS2PVETFRM =                0x110;  
static const unsigned WPULVETFRM =        0x114; 
static const unsigned HZ50VETFRM =        0x118;  
static const unsigned MSMVETFRM =         0x11C;  
static const unsigned EXTPEROVFVC =               0x120;  

static const unsigned EXT0VETFRM =        0x130;
static const unsigned EXT1VETFRM =        0x134;
static const unsigned EXT2VETFRM =        0x138;
static const unsigned EXT3VETFRM =        0x13C;

static const unsigned FC0VETFRM =                 0x150;        
static const unsigned FC1VETFRM =                 0x154;        
static const unsigned FC2VETFRM =                 0x158;        
static const unsigned FC3VETFRM =                 0x15C;        

// get 210 ns for free
// must have at least 1 us delay 
static const unsigned FSDELAY =               0x200; 

// these are for the MAPS fast fermi chopper veto
// all widths and delays are in 20ns steps
// all registers are 32 bit, big endian
static const unsigned FC0WINDLY =                 0x204;        
static const unsigned FC0WINWTH =                 0x208;        
static const unsigned FC1WINDLY =                 0x20C;        
static const unsigned FC1WINWTH =                 0x210;        
static const unsigned FC2WINDLY =                 0x214;        
static const unsigned FC2WINWTH =                 0x218;        
static const unsigned FC3WINDLY =                 0x21C;        
static const unsigned FC3WINWTH =                 0x220;        

// This pair form a 64bit counter running continuously at 50Mz (20ns steps)
// In event mode, this value is sent to each detector card for storage in frame header
static const unsigned FRAMETIME0 =              0x248;   
static const unsigned FRAMETIME1 =              0x24C;   


static const unsigned RVETO =                 0x40080;   
// veto enable register (40080) bits
static const unsigned RVFIFO =                    (1 << 0);
static const unsigned RVSMP =                     (1 << 1);
static const unsigned RVINT =                     (1 << 2);
static const unsigned RVFCHOP0 =                  (1 << 3);   
static const unsigned RVTS2P =                    (1 << 4);   
//static const unsigned RVWP =                    (1 << 5);   ///< wrong pulse
static const unsigned RVHZ50 =                    (1 << 6);   
static const unsigned RVMSM =             (1 << 7);   
//static const unsigned RVEXTPOVF =         (1 << 8);   ///< external period overflow
static const unsigned RVEXT0 =            (1 << 12);   
static const unsigned RVEXT1 =            (1 << 13);   
static const unsigned RVEXT2 =            (1 << 14);   
static const unsigned RVEXT3 =            (1 << 15);   
static const unsigned RVFCHOP1 =                  (1 << 21);   
static const unsigned RVFCHOP2 =                  (1 << 22);   
static const unsigned RVFCHOP3 =                  (1 << 23);   

static const unsigned   RCONTROL =            0x40084;  

// run control register bits (RCONTROL 40084)
// All are active high
static const unsigned   RCSTART =                   (1 << 0);   
static const unsigned   RCFCLEAR =          (1 << 1);   
static const unsigned   RCPCLEAR =          (1 << 2);   
static const unsigned RCPERSZEQZERO =   (1 << 3);    
static const unsigned RCEVENTMODE =             (1 << 4);    

static const unsigned RCFSSEL0 =                (1 << 16);  
static const unsigned RCFSSEL1 =                (1 << 17);      
static const unsigned RCFSSEL2 =                (1 << 18);      

static const unsigned RCDELFSFIFORS =   (1 << 14);      
static const unsigned   RCRESET =                   (1 << 15);  
static const unsigned   RCFSENABLEOUT = (1 << 20);      

static const unsigned RCFSSCH2 =                  (1 << 21);   

// frame sync select
static const unsigned RCFSSEL =                 (RCFSSEL0 | RCFSSEL1 | RCFSSEL2);       
static const unsigned RCFSINT =                 (0);                                                                            
static const unsigned RCFSSMP =                 (RCFSSEL0);                                                             
static const unsigned RCFSTOF =                 (RCFSSEL1);                                                             
static const unsigned RCFSMUONCK =              (RCFSSEL0 | RCFSSEL1);                                  
static const unsigned RCFSMUONMS =              (RCFSSEL2);                                                             
static const unsigned RCFSTOF1P =               (RCFSSEL0 | RCFSSEL1 | RCFSSEL2);               


struct veto_detail
{
        const char* name;
        unsigned mask;
        unsigned counter_addr;
        bool pc_only;           // veto counter only present on period card
};


static const veto_detail veto_details[];

static const unsigned MAX_NUM_PERIODS = (16*1024); 



// all 32 bit aligned addresses
// first period is number 0
static const unsigned   MPCNT =                   0x300;         
static const unsigned MPLIM =                     0x304;  
static const unsigned PSCNT =                     0x308;  
static const unsigned PSLR =                      0x30C;  
static const unsigned PERINCTOT =                 0x310;  
//static const unsigned I50HZVC0                  0x78;  ///< isis not at 50Hz veto count low (16 bit, RO)
//static const unsigned I50HZVC1                  0x7C;  ///< isis not at 50Hz veto count high (16 bit, RO)
//static const unsigned EXTPTRANVC0               0x80; ///< external period transition veto counter low (16 bit, RO)
//static const unsigned EXTPTRANVC1               0x84; ///< external period transition veto counter high (16 bit, RO)
static const unsigned PEROUTDEL =                 0x314;  
static const unused_t LOOKTAR =                   UNUSED_REGISTER;                       
static const unsigned PCREG =                     0x40088;  
//static const unsigned EXTPERREG                 0x4008c  ///< external periods register (16bit, RW) - see below
static const unsigned ALT1SFV =                   0x7FFF8;      

static const unsigned PERLUTSTART =               0x20000000;  
static const unsigned PERLUTSIZE =                (16*1024);  
static const unsigned PERLUTEND =                 (PERLUTSTART + 4*PERLUTSIZE);
static const unsigned OUTLUTSTART =               0x22000000;  
static const unsigned OUTLUTSIZE =                (16*1024);  
static const unsigned OUTLUTEND =                 (OUTLUTSTART + 4*OUTLUTSIZE);
static const unsigned OUTLUTMASK =                0xffffffff; 
static const unsigned RFCNT0START =               0x24000000; 
static const unsigned RFCNT0SIZE =                (16*1024);
static const unsigned GFCNT0START =               0x25000000; 
static const unsigned GFCNT0SIZE =                (16*1024);
static const unsigned RPCNT0START =               0x26000000; 
static const unsigned RPCNT0SIZE =                (16*1024);
static const unsigned GPCNT0START =               0x27000000; 
static const unsigned GPCNT0SIZE =                (16*1024);
static const unsigned RPCNT1START =               0xffffffff; 
static const unsigned RPCNT1SIZE =                0;
static const unsigned GPCNT1START =               0xffffffff; 
static const unsigned GPCNT1SIZE =                0;
static const unsigned SPARE0START =               0xffffffff; 
static const unsigned SPARE0SIZE =                0;
static const unsigned SPARE1START =               0xffffffff; 
static const unsigned SPARE1SIZE =                0;
typedef uint64_t ppp_memory_t;

// bits for lookup table access register (LOOKTAR, 0x40000)
// All are active high and allow writing to area
static const unsigned TARPERLUT =               (1 << 0); 
static const unsigned TAROUTLUT =               (1 << 1); 
//static const unsigned TARCNT0                 (1 << 2) ///< access Counts0 enable bit, RW
//static const unsigned TARBCT1                 (1 << 3); ///< access Counts1 enable bit, RW

// bits for period control register (PCREG, 0x40088)
// All are active high
static const unsigned PCENDAFTER =              (1 << 1);       
static const unsigned PCSEQCOMP =               (1 << 2);    
static const unsigned PCENDSEQCOMP =    (1 << 3);    
static const unsigned PCENAB =                  (1 << 4);    
static const unsigned PCEXTENAB =               (1 << 5);    
static const unsigned PCMULENAB =               (1 << 6);    
static const unsigned PCMULCOMP =               (1 << 7);    
//static const unsigned PCEXTPERCLK     (1 << 8);   ///< internal/external period clock mode enable (RW)
//static const unsigned PC50HZENAB      (1 << 9);    ///< isis not at 50 Hz veto enable (RW)
//static const unsigned PCEXTTRIG               (1 << 10);   ///< extract trigger veto enable (RW)
static const unsigned PCMSM =                   (1 << 11);      
//static const unsigned PCCLRVETO               (1 << 12);   ///< clear veto counters (RW)
static const unsigned PCCLRPC =                 (1 << 13);   
static const unsigned PCRESET =                 (1 << 15);   

// bits for perlut
static const unsigned PERLUTTYPE =                (1U << 31); 

};


#endif /* ENV_PERIOD_REGISTERS_DAE3_H */